Verilog

Verilog is a hardware description language with a C-like syntax, widely used to design and verify digital circuits, processors and FPGAs. Its SystemVerilog variant extends verification. With VHDL, it dominates electronic design.

• Creado por Phil Moorby & Prabhu Goel
• Año 1984
• Paradigma: Hardware description · concurrent
• Extensiones: .v, .sv

Para qué se usa

• Chip design
• FPGA
• Hardware verification

A favor

• C-like syntax
• Industry standard
• Powerful SystemVerilog

En contra

• Unintuitive concepts
• Hardware-only
• Complex debugging

Ecosistema

• Icarus Verilog
• Verilator
• SystemVerilog
• ModelSim

Ejemplo

module hola;
  initial begin
    $display("¡Hola, mundo!");
  end
endmodule